BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20211208T164408Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211207T163000
DTEND;TZID=America/Los_Angeles:20211207T173000
UID:dac_DAC 2021_sess261_DESPOST102@linklings.com
SUMMARY:CANCELLED End-to-End Solution for structured implementation of hig
 h-speed data buses
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nCANCE
 LLED End-to-End Solution for structured implementation of high-speed data 
 buses\n\nBehera, Agarwal, Rai, Tuteja\n\nHigh-speed buses require multi-st
 age pipeline repeater flops to travel large distance (> 10mm) in complex S
 oCs (size > 200mm2). Meeting stiff performance targets (1Ghz+) on these bi
 directional busses across PVT corners is highly challenging. Standard EDA 
 tools do not offer complete solutions and requires user intervention at va
 rious stages\n\nThis paper proposes an automated solution for structured p
 lacement of repeater flops along with a customizable clock tree with minim
 al user intervention. The solution works in 3 stages:\n1.	Intelligent plac
 ement of pipeline repeater flops, by assessing the distance between ports 
 and direction of data flow.\n2.	Ladder style clock tree structure provides
  a skew gradient across repeater flop groups.\n3.	Buses are trunk routed i
 n a controlled manner to optimize routing resources and crosstalk.\nThe au
 tomation helped in predictable convergence and reducing timing eco cycles.
 \nThis solution is independent of technology nodes and is flexible & easil
 y deployable.\n\nVirtual Program: Presented In-Person
END:VEVENT
END:VCALENDAR