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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164408Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211207T163000
DTEND;TZID=America/Los_Angeles:20211207T173000
UID:dac_DAC 2021_sess261_DESPOST131@linklings.com
SUMMARY:Robust Timing Analysis And Optimization under Parametric On-Chip P
 rocess Variation
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nRobus
 t Timing Analysis And Optimization under Parametric On-Chip Process Variat
 ion\n\nChai\n\nDesign considering variation is required in order to maximi
 ze profit and improve PPA because variation impact is increased in the dee
 p-sub micron technilogies  The existing POCV method to deal with variation
  doesn't consider block level timing impact while it applies variation imp
 act on each path. In this study, we propose a methid to analyze and optimi
 ze the timing impact due to variation at the block level.\n\nVirtual Progr
 am: Presented In-Person
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