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DTSTAMP:20211208T164408Z
LOCATION:DAC Pavilion
DTSTART;TZID=America/Los_Angeles:20211207T163000
DTEND;TZID=America/Los_Angeles:20211207T173000
UID:dac_DAC 2021_sess261_DESPOST175@linklings.com
SUMMARY:Algorithm to RTL: A Faster Path to Implementation
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nAlgor
 ithm to RTL: A Faster Path to Implementation\n\nKlein, Saha\n\nWhen design
 ing hardware, logic designers often need to implement an algorithm where a
  reference implementation exists as a software function.  High-level Synth
 esis (HLS) is an approach that converts an algorithm’s C/C++ implementatio
 n to a synthesizable hardware description.  However, to get a good hardwar
 e implementation the developer needs to introduce parallelism and concurre
 ncy to the algorithm, while considering the area impacts of each modificat
 ion.  This requires a deep understanding of the algorithm and of the trans
 formations that the HLS compiler performs while generating the hardware im
 plementation from the input code.  This can be daunting for even expert de
 signers.  Gaining an understanding of the data dependencies and opportunit
 ies for parallelism in a software implementation by “staring at the code” 
 is inefficient and impractical. Furthermore, going through an iterative sy
 nthesis and performance evaluation flow is extremely time consuming. We in
 troduce an approach that analyzes the input algorithm to determine the cha
 racteristics needed for a good HLS implementation. This data is used to cr
 eate  configuration files and code annotations to steer the HLS compiler, 
 without the developer needing an intimate understanding of the reference i
 mplementation.  An evaluation with a set of representative kernels showed 
 gains between 5-600x, when compared with a sequential HW implementation.\n
 \nVirtual Program: Presented In-Person
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