Session

DescriptionThis session covers the topic of intellectual property protection through piracy detection and secure design flow using high level synthesis tools and emerging devices. The presenters will discuss state of the art graph neural network-based piracy detection schemes, the implementation of side-channel attack resilient domain-oriented masking using high-level-synthesis to improve design time, and the security of hardware IP using emerging spin-based devices that utilize reconfigurable IP blocks. In addition, the use of architectural features for resource binding will be discussed as a means to enhance SAT resilience.