Session

DescriptionWith the increasing complexity of systems-on-chip (SoCs), developing efficient SoC design-space exploration methodologies has become challenging. This session presents six papers with novel contributions in the development of HDL framework for SoCs and improvement in SoC performance for acceleration. The first two papers focus on the behavioral design of SoCs and improve their performance for DNN acceleration. The third and fourth papers present co-exploration solutions and structural compilers for SoC-based accelerators. Finally, the last two papers propose new automated-design frameworks for hardware.