Session
Learning to Accelerate Circuit Timing Analysis
Event TypeResearch Manuscript
Hosted in Virtual Platform
Digital Design, Timing and Simulation
EDA
Time
Location
DescriptionThis session presents advanced methods for circuit timing analysis and optimization. The first two papers use new algorithms, data structures, and machine-level optimizations for improving the efficiency of common path pessimism removal (CPPR) problem and path-based timing analysis. The last two papers use machine learning techniques for learning resistor networks from linear measurements and for gate sizing.