Session

DescriptionDue to the lack of standard tools, methods, or solutions currently in practice, there is an urgent need for developing chip-level security solutions. The primary reason for the lack of security features in a chip has resulted from the economic hurdles and technical trade-offs often associated with chip design. This special session will highlight these concerns and opportunities. The first presentation will be an overview of the benefits of the security-aware CAD flows and discuss the attack surfaces such as side-channel attacks, reverse engineering, supply chain attacks, and malicious hardware attacks that need to be addressed. The second talk will focus on Security-Aware Computer-Aided Electronic Design Tools. The third talk will focus on Independent Verification & Validation (IV&V) of Security-Aware CAD tools. The final talk will discuss the Integration of IC Design Changes into a BlockChain for Traceability in the Electronic CAD Flow.