Input Qualification Methodology Helps Achieve System Level Power Numbers 8x Faster
TimeTuesday, December 7th5:00pm - 6:00pm PST
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
In-Person Only
DescriptionAn automated Input Qualification Methodology is proposed that performs various Data Integrity Checks at design build and prototype stage and ensures in quicker iterations that input data is high fidelity leading to a well correlated power numbers. If multiple retries are needed, checkpoint database method is implemented to bypass the clean stages of the tool run.
Various checks pertaining to activity annotation (FSDB/SAIF/STW/QWAVE), technology libraries (.lib) and parasitic (SPEF) mapping are already part of the tool. Defining an input qualification methodology around these checks can save up to 88% of project time in achieving reliable power numbers.