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Presentation

Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip
TimeTuesday, December 7th10:30am - 10:52am PST
Location3016
Event Type
Research Manuscript
Virtual Programs
Presented In-Person
Keywords
In-Package and On-Chip Communication and Networks-on-Chip
Topics
EDA
DescriptionIn this paper, we present a topology agnostic approach to solving the VC assignment problem. This segregation enables us to solve the VC
assignment problem before topology generation. We model the VC assignment problem as a traffic conflict graph (TCG), capturing a global view of Quality of Service (QoS), Head-of-Line (HoL) conflicts, burstiness and external protocol level dependencies (e.g. PCIe root-complex). We apply combinatorial optimization technique(s) on the TCG to arrive at an efficient VC assignment that ensures deadlock free designs. Results obtained on several multi-million gate production-grade SoC designs demonstrate an average improvement of 30% across various metrics.