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Session

Designer, IP and Embedded Systems Track Presentations: Novel Methods for Clocking and Functional Safety
Event TypeDesigner, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Front-End Design
Time
Location
DescriptionClocking continues to be an important aspect of chip development, end to end functional safety is increasingly becoming more important. This session explores novel methods in both of these important aspects of chip design.
Presentations
Practical Method for Clock Domain Crossing Using Simulation-Based Path Extraction
Presenter(s)
YoungRok Choi
Hyungjung Seo
So-Jung Park
ByongWook Na
Younsik Park
Jung Yun Choi
Hosted in Virtual Platform
A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization
Presenter(s)
Hao Chen
Ang Li
Suhas Prahalada
Howard Yang
Miguel Gomez-Garcia
Jonathan E. Schmidt
Leo Sporn
Hosted in Virtual Platform
Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Presenter(s)
Jae-Gon Lee
Wookyeong Jeong
Jaeyoung Lee
Byung Su Kim
Se Hun Kim
Young Duk Kim
Youngsan Kim
Yonghwan Kim
Sung Hoon (Ryan) Shim
Byeongho Lee
Jong-Jin Lee
Hoyeon Jeon
Younsik Choi
Joonseok Kim
Hosted in Virtual Platform
Accelerating mutation coverage measurement by using concurrent fault simulator
Presenter(s)
Kota Sakai
Kenichi Otsuka
Fumitaka Fukuzawa
Shintaro Imamura
Hosted in Virtual Platform
Analog Fault Simulation for Automotive Sensor Designs
Presenter(s)
Soohyun Kim
Yun Heo
Seokyong Park
Seongyeop Park
Ilryong Kim
Sungjin Park
Kwangsoo Seo
Hosted in Virtual Platform
Efficient Data Exchange Towards Faster Functional Safety Development
Presenter(s)
Shivakumar Chonnad
Vladimir Litovtchenko
Hosted in Virtual Platform