Session
Designer, IP and Embedded Systems Track Presentations: All Routes Lead to Closing Timing
Event TypeDesigner, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Back-End Design
Location
DescriptionTiming closure is the final stage of physical implementation, and where some of the most complex challenges can be encountered, creating critical schedule risk. This session covers methods to help ease timing closure, including optimization of routing layer usage, removal of pessimism from margins, quick/accurate parametrized block placement, and accelerated hierarchical ECO generation.
Presentations
| Enabling Hierarchical Flattened Functional ECO Flow for Quality Patch Generation with Runtime Benefits Presenter(s) | Hosted in Virtual Platform | ![]() ![]() |
| Middle of Layer Routing Enablement for Increasing Routing Resource | Hosted in Virtual Platform | ![]() ![]() |
| Methodology for Accurate Analysis of Dynamic Voltage Drop Induced Clock Jitter for Improved PPA Presenter(s) | Hosted in Virtual Platform | ![]() ![]() |


