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Session

Designer, IP and Embedded Systems Track Presentations: Tune in to the Clocks!
Event TypeDesigner, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Back-End Design
Time
Location
DescriptionClock design continues to be an important aspect of the overall chip design. In this session, you would come across some novel techniques used to resolve challenges in clock design during chip development.
Presentations
On-Chip Dynamic IR Drop Induced Deterministic Jitter Analysis
Presenter(s)
Dongchul Kim
Hosted in Virtual Platform
Optimal Function Clock Aware Scan Methodology
Presenter(s)
Chen Yuan Kao
Min Hsiu Tsai
Hosted in Virtual Platform
Accurate glitch noise analysis considering impact of secondary aggressors
Presenter(s)
Hyungoo Kim
Hosted in Virtual Platform