Session

DescriptionThe session presents reliability attacks in hardware design and proposes new methodologies for trustworthy fabrication. Get more insights into the Rowhammer vulnerability and its state-of-the-art variants by delving into a quantitative analytical model of capacitive-coupling weaknesses in DRAM. Learn about a new logic locking methodology which leverages high-level synthesis to protect IPs while mitigating attacks and minimizing area overhead and key size. Recent advances in Delay-PUFs are further analyzed to expose new modelling attacks that break previous security claims. Finally, a technique to fortify RTL locking techniques with scan-based functional mode isolation helps protect your keys along with your IP.