Research Manuscript: Tales of Memory, Latency, and Energy Optimizations
Event TypeResearch Manuscript
Hosted in Virtual Platform
Embedded System Design Methodologies
DescriptionThis session covers novel techniques for memory, latency, and energy optimizations in emerging processing chip platforms. The first paper proposes a co-design of OS and SSD that exploits the redundancy in transactional systems to cut ultra-dense SSDs’ read tail latency. The second paper proposes a hardware-friendly multi-stage Personalized Pagerank to minimize local latency with a tight memory budget through stage and linear decomposition. The third paper presents an information-theoretic framework that creates pareto-optimal resource management policies for mobile heterogeneous SoCs. The fourth paper tackles the problem of dynamic range growth for the efficient implementation of fixed-point FFT.