AMS Verification of HBMPHY: Challenges & Solutions - 12nm Process Node
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionWe will be presenting our work done on creating AMS verification setup that uses SV-UVM testbench for HBMPHY chip in 12nm technology node. The abstractions used in the design, viz., RTL and transistor level (TL) based on the design scope are discussed. In doing so, the challenges that we faced were two-fold. One was with respect to handling the intricacies involved in the integration of TL in a complex verification setup, such as SystemVerilog interface array elements connecting to TL (SV to Spice connection). Also, this is a multi-supply design operating at four different supply voltages, which added to the complexity in terms of associating each of the TL blocks with the correct supplies in such a complex setup. The other challenge was the simulation performance (runtime) bottleneck owing to huge number of IO cells with high frequency DLLs configured in TL. We were able to address these challenges and complete AMS verification of the chip by framing a mixed-signal verification (MSV) methodology that is discussed in this paper. The results thus obtained are captured and the runtime benefits are tabulated.