Performance Modeling of Digital Processing Systems
TimeMonday, December 6th10:50am - 11:10am PST
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
Embedded Systems
DescriptionPerformance modeling of complex and large processing systems containing multiple processors, shared memories and multiple application threads remain inadequate. Conventional modeling approach to predict performance early in architecture phase relies on modeling methodology utilizing languages like SystemC are complex and yet yield inaccurate performance data.
This paper proposes tools and methodology for architecture modeling and performance analysis by adopting data flow approach. The modeling approach decouples functionalities and timings thereby significantly reducing complexity. Instead of executing functionally correct software, it performs statistical analysis of software instructions. Besides predicting performance, the model also provides high confidence hardware and software design constraints.