DescriptionConnected chips in portable devices shall both be safe and secure. Therefore, they must be endowed with specific hardware to detect hazards and attacks. Industry recognized standards specify requirements in this respect: IEC 61508, ISO 26262 regarding functional safety, and FIPS 140 version 3 regarding cyber-security.
At the same time, chips at end-point (CPS, IoT, M2M, automotive, etc.) face challenging constraints, especially low of cost and low time-to-market.
This presentation highlights an integrated sensor, amenable to being deployed within chips in several copies interleaved with the design it detects faults in. The three main innovations of this sensor are: i) a front-end integration (owing to sensor being implemented in standard cells), ii) a wide range of abnormality detections (temperature, voltage, glitches, etc.) and iii) a low false positive rate made possible by a machine learning analysis of several sensors to make one accurate decision.
The machine learning part is integrated (50 kGE for 16 sensors) in logic, and detects the faults in 1000 clock cycles. In addition, the ML engine is able to classify the issue: attack vs hazard, and nature of "glitch" (electromagnetic, clock, etc.)