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Presentation

ECO patch generation & stitching to facilitate concurrent ECOs in High Performance Processor Designs
TimeWednesday, December 8th11:10am - 11:30am PST
Location2008
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
Topics
Back-End Design
DescriptionAs design sizes increase, the number of last minute changes(ECO) and the time required to process them(TAT) also increase. During the fag end of the design cycle owing to the congestion a small change can lead to massive impact in terms of timing & routing resources & can greatly hamper chip schedules. So, when multiple last minute changes arrive it is necessary to categorize must haves, good to haves & determine the implementable ones & apply the ECO change. As multiple ECOs arrive over a period it becomes TAT inefficient to apply ECOs sequentially for evaluation & ECO application. So, there is a need for a methodology to facilitate concurrent processing of individual ECOs to determine ECO acceptability & an ability to merge accepted ECO changes. This presentation describes a tool (mdiff) and a methodology (ECO stitching) to allow unrelated ECOs on a design to be implemented in parallel on copies of the design and then applied to single copy for reduced TAT.