Session
Learning to Accelerate Circuit Timing Analysis
Session Chair
Event TypeResearch Manuscript
Presented In-Person
Digital Design, Timing and Simulation
EDA
TimeWednesday, December 8th2:35pm - 3:00pm PST
Location3016
DescriptionThis session presents advanced methods for circuit timing analysis and optimization. The first two papers use new algorithms, data structures, and machine-level optimizations for improving the efficiency of common path pessimism removal (CPPR) problem and path-based timing analysis. The last two papers use machine learning techniques for learning resistor networks from linear measurements and for gate sizing.
Presentations
| 2:35pm - 2:57pm PST | RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning |