Research Manuscript: Exploit your modules for complete verification
Event TypeResearch Manuscript
Design Verification and Validation
TimeWednesday, December 8th10:30am - 11:30am PST
DescriptionThis session presents innovations that can boost effectiveness, specificity, automation, and confidence in module-level verification. It contributes an efficient test-generation algorithm for dynamic verification of DRAMs based on deep reinforcement learning and a method based on graybox fuzzing for effective and rapid test generation targeting specific module instances in large RTL designs. The session then proceeds with a tool for automatically constructing formal testbenches using SystemVerilog assertions to aid verification of the control logic governing the interactions between design modules. Finally, it offers a system for efficiently certifying the correctness of first-order logic proofs in satisfiability modulo theories solvers.