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Session

Research Manuscript: Verification is running: what are the next stops?
Event TypeResearch Manuscript
Virtual Programs
Presented In-Person
Keywords
Design Verification and Validation
Topics
EDA
TimeWednesday, December 8th11:30am - 12:00pm PST
Location3016
DescriptionThis session features advances in verification and testing to address increasing system complexity, security and emerging technologies.
It first proposes abstractions and mechanisms to detect bugs and vulnerabilities at system-level.
To this aim, trace notation for ISA definition is proposed for capture processor behaviors, while efficient extraction of reset-controlled events and concolic testing are used for detecting security vulnerabilities in SoC with asynchronous partial reset.
The session also addresses emerging directions in the verification of control systems based on neural networks and equivalence checking of quantum circuits. This is achieved by synthesizing barrier certificates of closed-loop systems controlled by neural networks and by employing tensor network contraction for computing the fidelity between an ideal quantum circuit and its noisy implementations.