Session
Tune in to the Clocks!
Session Chair
Event TypeDesigner, IP and Embedded Systems Track Presentations
Presented In-Person
Back-End Design
TimeWednesday, December 8th10:30am - 11:30am PST
Location2008
DescriptionClock design continues to be an important aspect of the overall chip design. In this session, you would come across some novel techniques used to resolve challenges in clock design during chip development.
Presentations
| 10:30am - 10:50am PST | Using Clock Skew to Fix Hold: A Path-Depth Based Useful-Skew Approach to Reduce Hold Buffer Insertion Presenter(s) | |
| 10:50am - 11:10am PST | Clocking Methods with Focus on PCIe Gen4 | |
| 11:10am - 11:30am PST | ECO patch generation & stitching to facilitate concurrent ECOs in High Performance Processor Designs |