Session
All Routes Lead to Closing Timing
Session Chair
Event TypeDesigner, IP and Embedded Systems Track Presentations
Presented In-Person
Back-End Design
TimeMonday, December 6th1:30pm - 2:30pm PST
Location2008
DescriptionTiming closure is the final stage of physical implementation, and where some of the most complex challenges can be encountered, creating critical schedule risk. This session covers methods to help ease timing closure, including optimization of routing layer usage, removal of pessimism from margins, quick/accurate parametrized block placement, and accelerated hierarchical ECO generation.
Presentations
| 1:30pm - 1:50pm PST | Methodology for early timing and floorplanning closure in custom circuit design | |
| 1:50pm - 2:10pm PST | Routing layer re-optimization in Physical Synthesis | |
| 2:10pm - 2:30pm PST | Aging Timing Analysis Based on EMPYREAN-XTime |