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Networking Reception, Work-in-Progress Poster: Networking Reception & Work-In-Progress Poster Session
Event TypeNetworking Reception, Work-in-Progress Poster
Virtual Programs
Presented In-Person
TimeWednesday, December 8th6:00pm - 7:00pm PST
LocationLevel 2 - Lobby
Presentations
CANCELLED: ARGOS: an Adaptive and ReGion-scale knowledge distillation for Object recognition Systems
Determining the Multiplicative Complexity of Boolean Functions using SAT
An Efficient Cell Capacitor Compact Modeling and Application for High-speed DRAM Design
A Coordinated GPU Overdrive Fault Attack on Neural Networks
FASCINET: Fully Automated Single-Board Computer Generator Using a Neural Network Based Datasheet Scrubber
Finding Optimal Implementations of Non-native CNOT Gates using SAT
Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing
Glitch and Level Detection Algorithms for Analog Mixed-Signal Verification Coverage Management
GridNetOpt: Fast Full-Chip EM-Aware IR Drop Constrained Power Grid Optimization via Deep Neural Networks
CANCELLED: IO Performance Modeling for Communication Workloads
On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies
Parameter Approximation in CNNs for Improved Inference on FPGA
A Robust DNN Accelerator with Data-path Fault Detection and Mitigation
CANCELLED: RoHNAS–When Robustness Meets HW-Aware NAS: A Neural Architecture Search Framework with Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks
RTL regression test selection using Machine Learning
Securing Deep Neural Networks Against Adversarial Attacks through Voltage Overscaling
CANCELLED: SonicFFT: A system architecture for ultrasonic-based FFT acceleration
SpecMCTS: Accelerating Monte Carlo Tree Search using Speculative Tree Traversal
Stimulus Truncation Method for Energy Efficient Memristor Based Neuromorphic Computing
Tatami: Dynamic CGRA Reconfiguration for Multi-Core General Purpose Processing
POSAR: A Flexible Posit Arithmetic Unit for RISC-V