Designer, IP and Embedded Systems Track Poster Networking Reception: Designer, IP and Embedded Systems Track Poster Networking Reception
Event TypeDesigner, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
TimeWednesday, December 8th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Algorithm to RTL: A Faster Path to Implementation
Attaining Consistent RTL Quality and Improving Development Cycles with GIT Continuous Integration Tools
Clocking Methods with Focus on PCIe Gen4
A flexible SAR-ADC IP for multiple technodes
ECO patch generation & stitching to facilitate concurrent ECOs in High Performance Processor Designs
Efficient High-Sigma Verification of Standard Cell Libraries
Enhanced Analytics and Reporting for Triage and Sign-off Timing
Enhanced Hyperscaling of Data Centers using In-Chip Monitoring & Sensing Fabrics
Expediting Data Converter Layouts using Design Planning & Analysis (DPA) Automation
Fast and Accurate DvD aware Timing Analysis
CANCELLED: Fast Tracking a Federal Authentication Solution for Secure Facilities
Hybrid Emulation Methodology for SSD Design
A Low Cost, Scalable and Predictable Gate Level Simulation Methodology for Giga-Scale SOCs
Machine learning Assisted Design Rule Debug and Rule Ranking Automation
CANCELLED: Modernizing Public Infrastructure with Interactive Devices
Multi-Physics Simulation Techniques toward Electromagnetic Side-Channel Attack Assessments on IC Chip Assembly
Optimizing hold eco using ML techniques
Pioneering Low Power Modeling and Verification Technique for custom blocks
Predicting Timing Bottlenecks in Place & Route using Machine Learning
Priority Synthesis in Physical Synthesis
CANCELLED: Rethinking New Product Introduction to Better Align to Client Needs
Robust Timing Analysis And Optimization under Parametric On-Chip Process Variation
Root-cause analysis of undefined slack using timing/netlist data model
Shift-left Post-Silicon verification with Speed and Accuracy
A Spring Model Approach For Timing Budget Apportionment
CANCELLED: Stress Testing to Survive an Industrial Gas Turbine
Using Clock Skew to Fix Hold: A Path-Depth Based Useful-Skew Approach to Reduce Hold Buffer Insertion