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Designer, IP and Embedded Systems Track Poster Networking Reception: Designer, IP and Embedded Systems Poster Networking Reception
Event TypeDesigner, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Presentations
Accelerating advanced node ramp up and robust Design Enablement for leading edge SoC designers
Accelerating Standard Cells Variation-Aware Characterization Methodology with Machine Learning Techniques
Accurate and efficient high-performance memory modeling for full-chip power noise analysis
AMS Verification of HBMPHY: Challenges & Solutions - 12nm Process Node
CANCELLED: Beyond Lint
Presenter(s)
Christmas Lights Displays As Embedded Systems
Presenter(s)
Cloud Infrastructure for Remote and Scalable EDA Hardware Training
Dual Feature Vector Hetero Graph Neural Network (DFV-GNN) based Post-Layout Parasitic Estimation
Presenter(s)
Early Layout Area and PLS Estimation by Designers
CANCELLED End-to-End Solution for structured implementation of high-speed data buses
Innovative Techniques to Accelerate Error Handling Verification of Complex Systems
MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
Memory Peripheral Standard Cell Architecture Optimization using DTCO under Strong Area Restriction
Methodology for early timing and floorplanning closure in custom circuit design
CANCELLED: Modernizing a Nationwide Indoor/Outdoor Package Sorting System
Presenter(s)
Multi-core System Verification Using Uvm Portable Stimulus​
New file system to automatically "spill" workloads across Datacenter and Cloud
MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows
Performance Modeling of Digital Processing Systems
PI Signoff Methods Used in a 5nm InFO Design
MOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor Design on the Cloud
CANCELLED: Resolution of Verification bottleneck by Functional Coverage Automation
RISC-V processor verification methodology with dynamic testbench for asynchronous events
Routing layer re-optimization in Physical Synthesis
SHIFT LEFT: NOVEL POWER ANALYSIS METHOD for LARGE-SCALE AI PROCESSORS
SoC Architectural Exploration for AI and ML accelerators with RISC-V
Updating RISC-V microarchitecture in the field through Menta co-extended cores and Codasip Studio
Utilizing the Cloud to Increase Library Characterization Throughput and Reduce Schedule Bottlenecks
Verification Methodology for High Resolution High Speed CMOS Image Sensor SoC - Leveraging Innovations in EDA Tools