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Designer, IP and Embedded Systems Track Poster Networking Reception: Designer, IP and Embedded Systems Poster Networking Reception

Event TypeDesigner, IP and Embedded Systems Track Poster Networking Reception

Virtual Programs

TimeMonday, December 6th5:00pm - 6:00pm PST

LocationLevel 2 - Exhibit Hall

Presentations

Accelerating advanced node ramp up and robust Design Enablement for leading edge SoC designers Presenter(s) Dipto Thakurta Pegah Hassanzadeh Joe Kwan Aliaa Kabeel Sarah Rizk Kareem Madkour Marwa Shafee Mostafa Alaa Michael Beshara Mohamed Ismail Yuyang Sun Jiechang Hou
Accelerating Standard Cells Variation-Aware Characterization Methodology with Machine Learning Techniques Presenter(s) Jean-Arnaud Francois Etienne Maurin Bastien Aghetti Rajnish Garg Honey Garg Austin Shirley Wei-Lii Tan
Accurate and efficient high-performance memory modeling for full-chip power noise analysis Presenter(s) Arif Mirza Girish Deshpande Santosh Santosh Karthik Srinivasan Rithunraj Krishna
AMS Verification of HBMPHY: Challenges & Solutions - 12nm Process Node Presenter(s) Vijaykumar Sankaran Santosh Mahadeo Narawade Shrikant Dhongadi
CANCELLED: Beyond Lint Presenter(s) Cedric Walravens
Christmas Lights Displays As Embedded Systems Presenter(s) James Roberts
Cloud Infrastructure for Remote and Scalable EDA Hardware Training Presenter(s) Matthew Morrison Owain Jones Kevin Dobie
Dual Feature Vector Hetero Graph Neural Network (DFV-GNN) based Post-Layout Parasitic Estimation Presenter(s) Sungwon Kim Hui Fu
Early Layout Area and PLS Estimation by Designers Presenter(s) Akshita Bansal Atul Bhargava Jonathan Longrigg Christian Symmons Paul Clewes
CANCELLED End-to-End Solution for structured implementation of high-speed data buses Presenter(s) Shubham Agarwal Subhadarshini Behera Dheeraj Tuteja Shishir Saran Rai
Innovative Techniques to Accelerate Error Handling Verification of Complex Systems Presenter(s) Bhushan Parikh Peter Graniello Neha Rajendra
MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs Presenter(s) Arun Joseph Spandana Rachamalla Shiladitya Ghosh Shashidhar Reddy Pradeep Joy Sampath Baddam Samuel Kirchhoff Joachim Fenkes Wolfgang Roesner
Memory Peripheral Standard Cell Architecture Optimization using DTCO under Strong Area Restriction Presenter(s) Seyong Ahn Joohan Kim SungHwan Cho SeungHyuk Kwon Youngmin Kim Younsik Park Hyuckjoon Kwon Jung Yun Choi JaeNyeong Kim
Methodology for early timing and floorplanning closure in custom circuit design Presenter(s) Geoffrey Wang Philip M. Bassett Tai Cao Saiful Islam Michael J. Lee Ryan Myers Hema Ramamurthy
CANCELLED: Modernizing a Nationwide Indoor/Outdoor Package Sorting System Presenter(s) Dale Hackathorn
Multi-core System Verification Using Uvm Portable Stimulus Presenter(s) Gaurav Gupta Arjun Singh Maninder Kumar Ajay Sharma
New file system to automatically "spill" workloads across Datacenter and Cloud Presenter(s) Alok Sinha Rajeev Prasad Jasmin Ajanovic
MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows Presenter(s) Arun Joseph Sampath Baddam Shashidhar Reddy Balaji Pulluru Pradeep Joy Ajay Gopalakrishnan Shiladitya Ghosh Arvind Haran Anthony Saporito Matthias Klein Wolfgang Roesner
Performance Modeling of Digital Processing Systems Presenter(s) Rajesh Chandra Deepak Shankar
PI Signoff Methods Used in a 5nm InFO Design Presenter(s) Ping Ding Junjie Chen Keqing Ouyang Chang Zhao Xin Yao Yao Liu
MOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor Design on the Cloud Presenter(s) Taeil Kim Naya Ha Jongho Kim Kyungtae Do Sangyun Kim
CANCELLED: Resolution of Verification bottleneck by Functional Coverage Automation Presenter(s) Shikhadevi Katharia Kiran Malvi Neil More Priyanka Gharat
RISC-V processor verification methodology with dynamic testbench for asynchronous events Presenter(s) Simon Davidmann Lee Moore
Routing layer re-optimization in Physical Synthesis Presenter(s) Nancy Zhou Lakshmi Reddy Alex Suess Cindy Washburn
SHIFT LEFT: NOVEL POWER ANALYSIS METHOD for LARGE-SCALE AI PROCESSORS Presenter(s) Shixuan Que Ling Sun Zhenhua Gan Cheng Peng
SoC Architectural Exploration for AI and ML accelerators with RISC-V Presenter(s) Simon Davidmann Duncan Graham Katherine (Kat) Hsu
Updating RISC-V microarchitecture in the field through Menta co-extended cores and Codasip Studio Presenter(s) Imen Baili Zdeněk Přikryl
Utilizing the Cloud to Increase Library Characterization Throughput and Reduce Schedule Bottlenecks Presenter(s) Kenneth Chang Dnyanesh Digraskar Matthieu Fillaud Wei-Lii Tan
Verification Methodology for High Resolution High Speed CMOS Image Sensor SoC - Leveraging Innovations in EDA Tools Presenter(s) Abhinav Agarwal Sumit Vishwakarma